1. Field of the Invention
The invention pertains to fabrication of semiconductor devices, and in particular, to bi-layer hardmasks that include a plasma-enhanced chemical vapor deposition (PECVD) layer such as PECVD silicon oxynitride (SiON).
2. Background Technology
Features of semiconductor devices such as gate lines are typically patterned using a bi-layer structure that serves as a bottom antireflective coating during photoresist patterning, and that further serves as a hardmask during patterning of an underlying patternable layer. FIG. 1 shows a structure that may be employed in such processing to form a gate line of a MOSFET. As shown in FIG. 1, a semiconductor substrate 10 includes isolations 12 that define an area in which a MOSFET is to be formed. A conformal gate insulating layer 14 such as silicon oxide is formed over the substrate 10 and oxides 12. A gate conductive layer 16 such as polysilicon is deposited over the gate insulating layer 14 and will be patterned to form a gate line. Formed over the gate conductive layer 16 is a bi-layer structure that serves as a bottom antireflective coating (BARC) and as a hardmask for patterning underlying layers. The bi-layer structure includes an amorphous carbon layer 18 and a PECVD SiON capping layer 20 having a thickness of approximately 260 angstroms. The amorphous carbon layer is doped with nitrogen to improve its etch selectivity with respect to the underlying polysilicon 16. A photoresist mask 22 is formed on the SiON capping layer 20. The photoresist mask 22 is used to pattern the SiON layer 20, which in turn is used as a hardmask to pattern the amorphous carbon layer 18, which in turn is used as a hardmask to pattern a gate line from the polysilicon layer 16.
As critical dimensions of semiconductor devices shrink, the dimensions of the structures used to pattern those devices are also reduced. In the case of the bi-layer structure of FIG. 1, this is seen as a decrease in the thicknesses of the SiON and amorphous carbon components of the bi-layer. At current dimensions, such thinning can produce detrimental effects. One source of detrimental effects is the presence of “pinholes” in the PECVD capping layer. Pinholes are believed to be formed by outgassing from underlying layers during deposition of the PECVD material. For example, when SiON is formed over an amorphous carbon layer, residual hydrogen may be emitted from the amorphous carbon layer. These emissions cause localized non-uniformities in the PECVD deposition plasma, which result in reduced deposition of SiON in the vicinities of the non-uniformities. Pinholes that extend partly or entirely through the SiON layer may form at those locations.
Pinholes are a source of at least two problems. One of these problems is photoresist poisoning. As shown in FIG. 1b, a pinhole 24 enables diffusion of nitrogen dopant from the amorphous carbon layer 18 into an overlying photoresist layer 26, forming a region of poisoned photoresist 28. Poisoned photoresist exhibits reduced response to conventional photoresist development chemistries, and as a result, unwanted photoresist bodies may be left behind after development, causing undesired patterning of underlying layers during subsequent processing.
A second problem caused by pinholes is premature etching of the amorphous carbon layer during reworking of photoresist. During typical processing, photoresist layers may be applied over a bi-layer hardmask, patterned, and removed several times. As shown in FIG. 1c, during removal of photoresist, the chemistry used to strip the photoresist may pass through a pinhole and contact the underlying amorphous carbon layer, causing etching of a region 30 in the amorphous carbon. This results in the formation of anomalous patterns in the amorphous carbon that may be transferred to underlying layers during subsequent processing. Such etching has been found to occur even with pinholes that do not extend completely through the SiON layer, a phenomena known as “punch through.”
Accordingly, there is a need for improved semiconductor processing techniques that reduce the detrimental effects of pinholes in PECVD materials.